The present invention relates to a fractional-N frequency synthesiser and to a transmitter including the fractional-N frequency synthesiser and can be applied to cellular radio applications such as GSM. The transmitter may comprise the transmitting section of a transceiver. The present invention also relates to an integrated circuit comprising the integratable components of the fractional-N synthesiser.
PCT Specification WO99/14859 discloses a sigma-delta modulator controlled phase locked loop (PLL) for use in a frequency synthesiser and/or to generate a phase modulated signal. This citation discloses a PLL comprising a frequency divider having a control input for a signal determining the division factor in the frequency divider. A sigma-delta modulator for generating a modulated signal has an output coupled to a digital filter for filtering the modulated signal and generating a filtered signal which is applied to the control input of the frequency divider. By filtering the output of the sigma-delta modulator, the quantization noise in the output signal produced by the sigma-delta modulator can be reduced within certain frequency regions. The reduction in quantization noise can, in turn, be traded for a reduced oversampling rate and/or decreased phase noise.
In implementing the cited PLL the coefficients of the digital filter are chosen such that its output is integer valued as long as its input is integered valued. This is said to be an important feature because the frequency divider can only deal with integer valued division factors.
In order for the digital filter to be able to carry out the operations described it is assumed that it is implemented as a Finite Impulse Response (FIR) filter having a large number of stages which are necessary to introduce zeros to reduce noise. However by having such a large number of stages there is an equally large number of division ratios in the divider of the PLL which, in turn, translates into a large frequency gain. This degrades the signal to noise (S/N) ratio at the output of the PLL as well as causing an increase in power consumption. The poor S/N ratio will be explained in the context of GSM which requires the frequency deviation to be xc2x167.7 kHz. The input to the sigma-delta modulator is a succession of positive, and negative voltages corresponding to Non Return to Zero (NRZ) bits. If the frequency gain of the PLL is large, then the input signal to the sigma-delta modulator has to be attenuated by the reciprocal of the gain. Since the output noise from the sigma-delta modulator is constant, this reduces the S/N ratio at the output of the PLL. The primary task of the digital filter is to reduce the noise by filtering but this effect is offset by the increase in PLL frequency gain caused by its very presence.
An object of the present invention is to provide a low noise fractional-N frequency synthesiser having a continuous tuning range which is greater than obtained with known PLLs.
According to a first aspect of the present invention there is provided a frequency synthesiser comprising a signal input, a sigma-delta modulator coupled to the signal input, a digital filter means coupled to an output of the sigma-delta modulator, and a phase locked loop(PLL) including a frequency divider having a control input coupled to an output of the digital filter means, characterised in that the frequency divider comprises a fractional divider and in that the filter means is configured to increase the number of output states by one over the number of input states.
According to a second aspect of the present invention there is provided a transmitter comprising digitising means for generating digitised signal input samples, a sigma-delta modulator coupled to a signal output of said digitising means, a digital filter means coupled to an output of the sigma-delta modulator, and a phase locked loop(PLL) including a frequency divider having a control input coupled to an output of the digital filter means, the PLL having an output for a signal at a frequency determined by the PLL, characterised in that the frequency divider comprises a fractional divider and in that the filter means is configured to increase the number of output states by one over the number of input states.
According to a third aspect of the present invention there is provided an integrated circuit comprising the frequency synthesiser in accordance with the first aspect of the present invention.
Compared to the arrangement disclosed in WO99/14859, the digital filter is a relatively basic FIR filter having say 2 stages which serves to increase the number of output states to 3 for an input having 2 possible states without disturbing the highly desirable spectral shape of the quantisation noise close to zero frequency. The filter in these circumstances produces no increase in the frequency gain of the PLL and consequently has an insignificant effect on the S/N ratio from the PLL. More significantly, the frequency synthesiser is able to operate on half ratios which have been found to give a 12 dB improvement in noise level and also continuous tuning can be achieved because successive groups of 3 half ratios can overlap.
The half radios allow the divider output phase to move through an integer multiple of xcfx80 radians before the ratio is changed rather than the 2xcfx80 radians as applied in the cited prior art. Hence in an embodiment of the present invention, the reference frequency of the PLL is half the clock frequency of the sigma-delta modulator. By halving the reference frequency it has been found that a 6 dB improvement in noise performance is obtained. Since another 6 dB improved is obtained from the step interval between the divider ratios, there is gained a 12 dB improvement in noise level compared to a situation where an adjacent pair of divider ratios is addressed directly by a 1-bit sigma-delta modulator.